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New approaches to a simulation-assisted design and process development

H. Walk, M. Schäfer, CADwalk - Design & Simulation, Allmendingen, Germany M. Glück , U. König, Daimler-Benz AG, Ulm, Germany
Fig1 - Current Density
Modern communication systems (e.g. satellite and mobile communication, GPS, super-fast microprocessors, DSP) require improved device and circuit performances at higher frequency ranges. They also demand development of novel transistors with low noise, improved current gain, and reduced power consumption, operating at frequencies in the GHz range. Simulating in a "Virtual Wafer Fab" [1] reduces time and costs in process, equipment, and device development; avoids the development of faulty prototype equipment; and offers yield optimization as well as significant reduction in the number of useless wafer batches. The efficiency and success of training courses for design and process optimization can be enhanced considerably by employing advanced simulation tools [2]. Visualizing the details of a fabrication step and entrie process, and the physical phenomena involved in the device operation gives immediate insight into a miniaturized device or circuit that is not always accessible by experimental diagnostics. For example, simulation can be show how various implantation energies and doses change the resulting device structure and how the affect the DC and RF performance. To answer such a question by real experimentation is very expensive, time consuming, and practically impossible.
New services to semiconductor industries
Reliable simulation requires a variety of input parameters but also supports process engineers. Cooperation between simulation experts and designers helps the designer to benefit from calculation and process design and forces him or her to see the design from a new perspective. The integration of electronic design automation (EDA), technology computer-aided design (TCAD), and advanced equipment simulation under one roof is one goal of simulation-assisted designs. The concept can be best demonstrated by the simulation-assisted development of new fabrication processes, such as advanced two-dimensional processes for Si/SiGe heterodevices, in collaboration with the Daimler-Benz research center. A complete simulation of the fabrication process sequence is essential. As a first example, take a conventional Si n-MOSFET self-aligned spacer process. All the key processes have been implemented in the SILVACO-ATHENA simulator [1] and adapted to the equipment that was available: gate oxidation, polysilicon deposition and subsequent anisotropic etching, PECVD-SiO2 deposition for the spacers, spacer etching in another anisotropic etch step, contact implantation, and subsequent rapid thermal annealing. The resulting device structure is then used to calculating the electrical characteristics using the SILVACO-ATLAS 2-dimensional device simulator [1]. Figure 1 illustrates the important details of a certain process sequence and the physical phenomena involved in the device operation at a specific biasing condition (e.g., VG = 3V, VDS = 5V). One can plot the carrier distribution in the implanted contact zones, the formation of ultrashallow junctions under the spacers, the formation of the inversion layer under the gate near the surface, or even a substrate leakage current. Figure 1 shows an enlarged cross-section of the important channel region beneath the gate. Normally, breakthrough due to high electric fields happens near the drain end of the channel. Under certain bias conditions there are higher electric fields near the source end that may affect device operation and the resulting manufacturing yield. High current densities and possible leakage paths are found immediately using simulation.
fig2 - Electric Field
Novel Si-based devices with record performance for high-speed operation
Device performance has improved continuously since the first demonstration of field-effect transistors (MESFETs and MOSFETs) Modulation-doped AlGaAs/GaAs heterostructure field-effect transistors were indroduced in 1980 [3]. Higher mobilities than in bulk material have been found in the quantum well channel, a two-dimensional electron gas (2DEG). This can be attributed to reduced Coulomb scattering in the presence of a spatial separation by a thin undoped spacer of free electrons in the 2DEG channel and locally fixed ionized donors in the supply layer. Different names for the same type of device exist, depending on the basic principles of operation, for example, "High Electron Mobility Transistor" (HEMT), "Modulation Doped Field-Effect Transistor" (MODFET) or "Two Dimensional Electron Gas FET" (TEGFET). The material system Si1-xGex is, so far, the only heterosystem that is compatible with Si devices and circuits. Thus novel Si/SiGe hetero-FETs may combine the advantages of heterodevices with well-established Si technology. The enormously improved DC and RF characteristics of Si/SiGe may lead to the development of new digital or analog devices and circuits operating at frequencies that are not available through conventional Si MOS technology [4-8]. Ultrafast devices and circuits for digital signals processing in information or sensor technology are only a small part of possible applications. The development of design rules, fabrication processes, and satisfactory transistor models for these CMOS-compatible devices and integrated circuits can only proceed quickly and effectively through the implementation of advanced powerful simulation tools. Figures 2and 3 show the footprint of a T-shaped 0.15 µm gate with a very low gate resistance and ohmic source, and drain contacts realized by phosphorous implantation and rapid thermal annealing. The heterostructure layer sequence and fabrication process are discussed in detail elswhere [5, 6]. Figure 2 shows the electric field distribution, especially beneath the gate, while Figure. 3 shows the current density. In the conducting strained Si layer, a 2DEG channel is sandwiched between two SiGe layers. The drain current (red regions) is mainly confined to the buried Si channel layer under on-state biasing condition and no significant gate leakage is observed. Hetero-FETs usually suffer from the formation of a parasitic MESFET in the doping layer under on-state bias condition (forward bias VG 0.6 V) because of a higher than necessary doping concentration in the supply layer.This parasitic channel (also seen in Fig. 3) affects the modulation efficiency significantly and can be avoided using advanced 2D simulation tools, such as SILVACO-BLAZE [1]. The contribution to the whole drain current in this structure is rather low, but further optimization seems to be possible.
Fig3 - Current Density
Trust in simulated processes and devices?
Many scientists have been skeptical of advanced process, device or equipment simulation tools. Is reliable process simulation really possible? Why not? Jet pilots and car drivers are trained in very complex simulators for their difficult job, why not training process engineers and designers through simulation? The excellent agreement between the calculated device characteristics (Figure 4) and experimental data, especially the transconductances and the maximum cut-off frequencies of oscillation (fmax) around 91GHz at supply voltages around VDS = 1.5 V [5, 6], confirm the succesful implementation of the simulation tools. (To the authors´ knowledge, 91 GHz is the highest fmax values published so far for all types of Si-based field-effect transistors.) On the other hand, the feasibility of this novel Si based device generation for low power digital and analog circuits design in the RF range is clearly demonstrated by the high cut-off frequencies.
Drain Current over Gate Voltage
Acknowledgments
Special thanks for valuable discussions and support to H. Marquardt and H. G. Sporrel from SILVACO International´s European head office in Munich. The financial support of this work by the German Bundesministerium für Bildung und Forschung within the project "Nano-MOS", grant M 2957, is gratefully acknowledged. ATHENA, ATLAS, and BLAZE are trademarked simulation tools developed by SILVACO International.

References

1. SILVACO International,Virtual Wafer Fab Interactive Simulation Tools for
Semiconductor Design Tools: ATHENATM Process Simulator, ATLASTM Device
Simulator, BLAZETM Heterostructure Simulation Tool.

2. G. Wachutka, P. Voigt, "Computer-Aided Training in Design and Fabrication of
Microdevices ans Systems", Proc. of the 3rd Intern. Conf. on Computer Aided
Engineering Education, pp. 345-350, 13.-15.9.1995, Bratislava.

3.  T. Mimura, S. Hiyamizu, T. Fujii, K. Nanbu, "A new field-effect transistor with
selectively doped GaAs/n-Al(x)Ga(1-x)As heterojunctions", Jpn. J. Appl. Phys.,
vol. 19 (5), pp. 225-227, 1980.

4. R. Hagelauer, T. Ostermann, U. König, M. Glück, G. Höck, "Performance
Estimation of Si/SiGe Hetero-CMOS Circuits", to be published in IEE Electronics
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5. M. Glück, T. Hackbarth, U. König, A. Haas, G. Höck, E. Kohn, "High fmax n-type
Si/SiGe MODFETs", accepted for publication in IEE Electronics Letters, Jan. 1997

6. M. Glück, T. Hachbarth, U. König, M. Birk, A. Haas, E. Kohn, " Depletion and
Enhancement Mode SiGe n-type MODFETs with fmax up to 92 GHz", submitted
to IEEE Electron Dev. Lett.

7. K. Ismail, "Si/SiGe High-Speed Field-Effect Transistors", Proc. of the IEDM´95, pp.
509-512, Washington, 1995.

8.  A.G. O´Neill, D. A. Antoniadis, "Deep Submicron CMOS Based on Silicon
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pp. 911-918, 1996
For more information, contact:
Michael Schäfer, CADwalk - Design & Simulation,
Joseph-von-Sontheimer-Strasse 3,
D-89604 Allmendingen, Germany;
ph 49/7391-7063-0, fax 49/7391-7063-11,

Figures Captions

Figure 1. Current densities of a self-aligned MOSFET in an enlarged cross-section under the gate. High current densities
Figure 2. Simulation of novel SiGe Hetero-FETs for high-speed application. Electric field distribution in an enlarged cross-section beyond the gate electrode. Indications of the complex structure consisting of various Si and SiGe layers are seen.
Figure 3. Current density plot of the same cross-section. Red regions with high current densities show that the drain current is mainly confined to the buried Si channel layer under on-state biasing condition and no significant gate leakage is observed. The inset of an unwanted parasitic channel that significantly affects the modulation efficiency can also be seen (green regions).
Figure 4. Simulated DC output characteristics of the modulation-doped SiGe Hetero-FET described before with transconductances up to 290 mS/mm.